(1) Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to the structure of a word-line discharging circuit using a PNPN element in a bipolar random access memory (RAM) device.
(2) Description of the Prior Art
Due to recent developments made in the technology of semiconductor memory devices, it has become necessary to increase the degree of integration of and to decrease the chip size of a high-speed bipolar semiconductor and MOS metal-oxide semiconductor (MOS) memory devices. The degree of integration of a MOS can be easily increased while that of a high-speed bipolar RAM device cannot. A high-speed bipolar RAM device is used especially as a working register in a central processing unit (CPU) of a large-scale electronic computer, etc. and is arranged in a high position in a memory hierarchy structure including low-speed, high-capacity memory devices and high-speed, low-capacity memory devices, i.e., in a position near an arithmetic circuit. A general-purpose, large-scale computer tends to use a parallel processing system or a multi-processing system, and the CPU thereof tends to be highly functional. In a CPU of future large-scale computers, it will be essential to integrate therein working registers at a high density. Therefore, it is necessary to increase the degree of integration of a bipolar RAM device while retaining the high-speed quality thereof. In a bipolar static RAM device, each of the static-type memory cells connected to word lines forms a type of capacitive load for a word line. Therefore, it is necessary to use word-line discharging circuits, each of which extracts a discharging current from a word line having a low potential so that electric charges are removed from the memory cells connected to a word line having a high potential when the word line having a high potential changes from a selected state to a non-selected state. It is also important that the degree of integration of the discharging circuits be large.
As is illustrated in FIG. 1, a conventional word-line discharging circuit uses a capacitor C having a large capacitance and resistors R.sub.1 and R.sub.2 having a large resistance. A discharging current flows for a predetermined period of time and is controlled by discharging the electric charges stored in the capacitor C through the resistors R.sub.1 and R.sub.2. In the discharging circuit 1 of FIG. 1, a word line W.sup.+, having a high potential and being connected to a static-type memory cell 2 of a static RAM device, is connected to the base of an emitter-follower transistor Q.sub.1, whose collector is connected to a high-voltage terminal of a voltage source V.sub.CC. The emitter of the transistor Q.sub.1 is connected to a constant-current source I.sub.1 via the resistors R.sub.1 and R.sub.2. The common connecting point of a series connection of the resistors R.sub.1 and R.sub.2 is connected to a terminal of the capacitor C having a large capacitance. Another terminal of the capacitor is connected to a low-voltage terminal of the voltage source V.sub. CC. The common connecting point of the resistors R.sub.1 and R.sub.2 is also connected to the base of a discharging transistor Q.sub.2. The collector of the transistor Q.sub.2 is connected to a word line W.sup.-, having a low potential, and to the memory cell 2, and the emitter thereof is connected to a constant-current source I.sub.2 for discharging a current.
In such a conventional discharging circuit using a capacitor C and resistors R.sub.1 and R.sub.2, when the word line W.sup.+ having a high potential changes from a selected state to a non-selected state, i.e., when the potential V.sub.W + of the word line W.sup.+ changes from high to low as illustrated in FIG. 2, the potential of the base of the discharging transistor Q.sub.2 does not change from high to low immediately. That is, in such a transient state, since a constant current flows through the emitter of the emitter-follower transistor Q.sub.1 into the constant current source I.sub.1, the potential of the emitter thereof is always lower than the potential of the word line W.sup.+ by a base-emitter forward-biased voltage of 0.8 V so that the potential of the emitter thereof falls immediately. However, the potential of the common connecting point of the resistors R.sub.1 and R.sub.2, i.e., the base of the discharging transistor Q.sub.2, does not fall immediately because the capacitor C having a large capacitance is connected thereto. The potential of the base of the transistor Q.sub.2 falls after the electric charges stored in the capacitor C are discharged through the resistors R.sub.1 and R.sub.2. Therefore, the collector current of the discharging transistor Q.sub.2 , i.e., the discharging current I.sub.W -, continues to flow for a short time when the transistor Q.sub.2 is in a turned-on state after the word line W.sup.+, having a high potential, has changed from high to low, as illustrated in FIG. 2. The discharging current from the word line W.sup.- is cut off when the transistor Q.sub.2 changes from a turned-on state to a turned-off state after a delay time T determined by the time constant of the discharging circuit. The conventional discharging circuit which operates in the above-mentioned manner uses a capacitor having a large capacitance and resistors having a large resistance. Therefore, if it is necessary to increase the time constant of the discharging circuit, the area occupied by the discharging circuit on a semiconductor chip becomes large, with the result that it is impossible to increase the degree of integration of a memory device using discharging circuits.